1. Field of the Invention
The present invention relates to a polysilicon flash electrically erasable programmable read only memory (i.e., flash EEPROM), particularly a flash EEPROM cell having two or three polysilicon layers, and methods of making same.
2. State of the Art
Electrically programmable ROMs (EPROMs) are memory devices which write data electronically using a technique known as hot electron injection. With hot electron injection, a floating gate is charged to a logic level high by energized carrier electrons. The high energy electrons are then able to pass through an insulator and into the floating gate.
A conventional drain side hot electron programmed EPROM requires a relatively large current for programming and an external high voltage power supply is required in addition to the standard five volt supply. This limits the number of memory cells which can be simultaneously programmed without exceeding the power limitation of the circuit. Further, the device has to be removed from the circuit board for UV erasure of the memory cells.
EPROMS utilizing source side injection can reduce the programming current to a lower level. Although this technology can provide a relatively high density memory and merely requires a standard five volt power supply, it still has to be removed from the circuit board for UV erasure.
The document entitled, "A Novel High-Speed, 5-Volt Programming EPROM Structure with Source-Side Injection," Wu et al., IEDM 86, 1986, pp. 584-587, discloses a conventional source-side injection EPROM (SIEPROM) wherein a high channel electric field is used to generate hot electrons. The high channel electric field is created near the source when a large gate voltage is applied so that both high channel and oxide field exist simultaneously.
FIGS. 1(a)-1(d) of the present application disclose processing steps for manufacturing a SIEPROM in accordance with the Wu document (see also U.S. Pat. No. 4,794,565 issued to Wu et al.). FIG. 1(d) shows a cross-section of an SIEPROM cell which includes a stacked-gate MOSFET with a side wall floating gate 25 (i.e., a polysilicon spacer) on the source side, flanking the stacked gate. A weak gap-controlled channel region is formed under oxide placed between the side wall gate and the stacked gates. By locating a high channel-field near the source, the local gate oxide field is favorable for hot-electron injection.
This SIEPROM cell structure has the advantage that it can be programmed with drain voltages as low as five volts. This five volt level is below the device breakdown level and therefore affords a large tolerance for process control and device design. It is also possible to program the cells with a single five volt power supply since a gate voltage of fifteen volts can be supplied by charge pumping circuitry. Further, even at a low programming voltage, the programming speed of the SIEPROM is faster than that of the drain side injection EPROMs. However, because EPROMs use ultraviolet (UV) light to erase stored data, inconvenient and time consuming removal of the EPROM from a circuit board is still required.
Electrically erasable PROMs (EEPROM or E.sup.2 PROM) are another variety of known memory devices. EEPROMs do not require a UV light source for erasure and do not necessarily require the memory device to be removed from the circuit board for reprogramming. However, EEPROMS require a select transistor for each memory cell. Accordingly, these devices are relatively large, thus limiting their usefulness in circuits requiring high density memory (i.e., large memory requirements in space limited circuit).
Typically, EEPROM cells are fabricated using metal oxide semiconductor field effect transistors (MOSFETs) as described in U.S. Pat. No. 4,477,883. As shown in FIG. 2(a) of the present application, an EEPROM memory cell is formed with a double layer of polysilicon and three electrodes electrically isolated from each other by oxide films. EEPROMs use this configuration to exploit the known phenomenon of electron tunneling during programming and erasure.
Referring to FIG. 2(a), a first electrode 11 is a floating gate completely encapsulated in an oxide insulating layer. A second electrode 12 is a tunneling gate. Electrons tunnel toward the electrode 12 through a tunnel oxide region 17 between field oxide layers 15 interposed between the electrodes 11 and 12. A third electrode 13 is a coupling gate. The floating gate 11 is capacitively coupled to the coupling gate 13. The combination of the coupling gate 13, the floating gate 11 and the tunneling gate 12 can be represented by the two series connected capacitors shown in FIG. 2(b).
The tunneling gate 12 and the coupling gate 13 control the charge and discharge (programming and erasure) of majority carriers (i.e., electrons) in the floating gate 11. The tunneling gates 12 in a line of memory cells are typically connected together to establish a column line, while the coupling gates 13 are typically connected together in a byte wide configuration.
When data is written into a memory cell, a relatively high voltage (e.g., 20 volts) is supplied via the column line to the tunneling gate 12. When the gate 12 of a cell located at the intersection of the row and column lines is placed at a high potential, a tunneling current flows through the tunnel oxide region 17. Electrons are thereby emitted from the floating gate 11 to write the logic level high.
To erase a logic level high, the coupling electrode 13 (normally kept low for writing operations) is raised to a logic level high while the tunneling gate 12 is placed at a low potential (e.g., ground). As a result, electrons tunnel upward and the floating gate 11 returns to a logic level low. In alternate embodiments, polysilicon-to-polysilicon tunneling has been used to remove floating gate electrons from the floating gate during an erasure mode.
A further development in semiconductor memory devices relates to the use of hot electron injection for programming an EEPROM. EEPROMs which use hot electron injection for programming and which use tunneling for erasure are sometimes referred to as flash EEPROMS.
A flash EEPROM which combines source side injection programming and electron tunnelling erasure has the advantages of high density, a single five volt power supply, and on board electrical programming and erasure. However, integration of a flash EEPROM cell to conventional CMOS fabrication processes can result in degradation of peripheral transistors. Peripheral transistors are, for example, desirable for use as memory control logic.
Because the processing steps currently used to fabricate known memory cells do not account for the fabrication of peripheral transistors on the same substrate, peripheral transistors formed on the same substrate as memory cells are often inferior devices. For example, the performance of the peripheral transistors is severely degraded by high temperature processing steps during fabrication of the memory cells. The inability to fabricate high quality peripheral transistors on a common substrate with memory cells limits practical implementation of the memory cells in an integrated circuit.